Senior Power Packaging Design Engineer (NPI & OSAT)

Renesas Electronics Corp.; Phoenix (AZ); On-site; USD 180,000 - 280,000; Full time

Job summary

Renesas Electronics Corp. in Phoenix, AZ seeks a senior packaging technologist to lead development for AI/datacenter power packaging and advanced interconnects, including SiC/GaN considerations.

You will manage OSAT/CM partners, drive DOE studies, and qualify new packages within aggressive timelines. Candidate should have 15–20 years in power package development, strong wafer-level/flip-chip expertise, and excellent analytical and presentation skills.

Qualifications

• Doctorate/Master’s / Bachelor’s Degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.
• 15 to 20 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip packaging
• Strong understanding of power SiP/modules, wafer level/flip-chip packaging methods, assembly process knowledge, qualification methods, SPC and statistical analysis software

Responsibilities

• Package Technology Development/NPI, R&D, Global OSAT management for new Package Development/Product qualification, Technology Roadmap definition, R&D budget management & customer adoption programs.
• Focus on design and development of package and interconnect methods for Renesas’s AI/Datacenter Infrastructure Power packaging needs especially Smart Power Stages, Vertical Power Stages, Power Modules & Discrete FET packages.
• Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).
• Work with OSAT/CM to develop, run DOE to optimize processes and establish process spec.
• Work with Product groups and Reliability team, qualify new packages and processes within required time frame.
• Resolve all process integration issues by ensuring all window checks are done on critical process steps.
• Establish production controls and monitors to ensure there is no room for quality incidents.
• Ensure smooth transition into production & implement ramp up monitor.
• Work with OSAT/CM to monitor and resolve process issues early in the production phase to ensure only parts with superior quality shipped to customer.
• Develop and maintain technical expertise on advances and innovations in power SiP/modules, wafer level packaging & flip chip interconnects.
• Participate in packaging roadmap development & focus on execution.
• Address internal and external customer complaints working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses.
• Establish & maintain package design rules.

Skills

Interpersonal skills

Analytical skills

Presentation skills

Education

PhD/MS/BSc in Physics or Engineering

Tools

SPC

Statistical analysis software

Job description

Renesas Electronics Corp. in Phoenix, AZ seeks a senior packaging technologist to lead development for AI/datacenter power packaging and advanced interconnects, including SiC/GaN considerations.

You will manage OSAT/CM partners, drive DOE studies, and qualify new packages within aggressive timelines. Candidate should have 15–20 years in power package development, strong wafer-level/flip-chip expertise, and excellent analytical and presentation skills.