Power SiP & Packaging Design Lead

Renesas; Tempe (AZ); On-site; USD 120,000 - 180,000; Full time

Job summary

Renesas is seeking a senior packaging engineer in Tempe to design and develop power SiP/module interconnects, WLCSP and multi-chip packages. You will work with wafer-level processes, Cu RDL and backside metal deposits, and coordinate with OSAT/CMs to optimize production and quality.

The role requires 10–15 years in package development, strong analytical skills, and the ability to drive DOE studies, qualification tests, and ramp-up activities across cross-functional teams.

Qualifications

• Doctorate/Masters / Bachelor’s Degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.
• 10-15 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip LGA packaging.
• Strong understanding of power SiP/modules which has an substrate or embedded die/capacitor, assembly process knowledge, qualification methods, SPC and statistical analysis software. Knowledge of Cu FSM/BGBM technologies a plus.

Responsibilities

• Design and develop package and interconnect methods for Renesas’s packaging needs in Power SiP/modules, WLCSP, and multi-chip module with substrate or embedded die/capacitor.
• Develop Cu RDL with seed layer on IC wafer and FET and Backside metal deposit after grinding.
• Wafer thinning development through Taiko BG and Glass carrier bond.
• Define substrate, die interconnection through via, materials and PCB interface requirements.
• Package technologies qualification for consumer & industrial power as well as automotive power applications.
• Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).
• Work with OSAT/CM to develop, run DOE to optimize processes and establish process spec.

Skills

Strong interpersonal and communication

Strong analytical and presentation

Education

Engineering degree (PhD/MS/BSc)

Job description

Renesas is seeking a senior packaging engineer in Tempe to design and develop power SiP/module interconnects, WLCSP and multi-chip packages. You will work with wafer-level processes, Cu RDL and backside metal deposits, and coordinate with OSAT/CMs to optimize production and quality.

The role requires 10–15 years in package development, strong analytical skills, and the ability to drive DOE studies, qualification tests, and ramp-up activities across cross-functional teams.