Director of Power Packaging Engineering (SiP/WLP)

Renesas; Phoenix (AZ); On-site; USD 180,000 - 240,000; Full time

Job summary

Renesas is seeking a seasoned packaging engineer to lead Package Technology Development/NPI and R&D for AI/datacenter power packaging, including Smart Power Stages, vertical power stages and power modules. The role focuses on wafer‑level, flip‑chip and multi‑chip module concepts with OSAT/CM coordination.

You will collaborate with Product, Quality and Operations to define processes, qualify new packages, and drive ramp‑up and production controls.

Qualifications

• 15–20 years in package development focusing on power SiP/module
• Deep knowledge of wafer‑level and flip‑chip packaging
• Experience with wire-bonding and module technologies is a plus
• Excellent communication and collaboration skills

Responsibilities

• Lead package development and NPI initiatives for AI/datacenter power packaging.
• Collaborate with OSAT/CM to define processes and specs.
• Drive production transition and ramp‑up monitoring.
• Develop and maintain technical expertise in power SiP/modules.
• Address internal/external customer issues with cross‑functional teams.

Skills

Power SiP packaging

Wafer level packaging

Flip-chip packaging

Wire-bonding

Analytical skills

Communication skills

Education

Engineering degree (PhD/MS/Bachelor)

Tools

SPC software

Statistical software

Job description

Renesas is seeking a seasoned packaging engineer to lead Package Technology Development/NPI and R&D for AI/datacenter power packaging, including Smart Power Stages, vertical power stages and power modules. The role focuses on wafer‑level, flip‑chip and multi‑chip module concepts with OSAT/CM coordination.

You will collaborate with Product, Quality and Operations to define processes, qualify new packages, and drive ramp‑up and production controls.