Director, Power Packaging & SiP Innovation

Renesas Electronics; Dallas (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

Renesas Electronics is seeking a senior package technology engineer in Dallas to lead R&D for power SiP/module packaging, wafer-level and flip-chip technologies, and collaboration with OSAT/CM partners. The role shapes packaging roadmaps and drives process improvements across global teams.

The candidate will manage DOE programs, drive qualification, and coordinate with Product and Reliability groups to meet aggressive timelines while maintaining high quality standards.

Qualifications

• Doctorate/masters/bachelor in engineering.
• 15–20 years in package development emphasizing power SiP/module.
• Strong understanding of power SiP/modules and wafer level/flip-chip packaging methods.
• Knowledge of wire-bonding & multi-chip module technologies.
• Strong interpersonal and communication skills.
• Strong analytical and presentation skills.

Responsibilities

• Package Technology Development/NPI, R&D, Global OSAT management for new Package Development/Product qualification, Technology Roadmap definition, R&D budget management & customer adoption programs.
• Focus on design and development of package and interconnect methods for Renesas’s AI/Datacenter Infrastructure Power packaging needs especially Smart Power Stages, Vertical Power Stages, Power Modules & Discrete FET packages.
• Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).
• Work with OSAT/CM to develop, run DOE to optimize processes and establish process spec.
• Work with Product groups and Reliability team, qualify new packages and processes within required time frame.

Skills

Interpersonal skills

Communication skills

Analytical skills

Presentation skills

Wire-bonding knowledge

Wafer level packaging

Flip-chip packaging

SPC & statistics

Education

Doctorate/Masters/Bachelor’s Degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering

Job description

Renesas Electronics is seeking a senior package technology engineer in Dallas to lead R&D for power SiP/module packaging, wafer-level and flip-chip technologies, and collaboration with OSAT/CM partners. The role shapes packaging roadmaps and drives process improvements across global teams.

The candidate will manage DOE programs, drive qualification, and coordinate with Product and Reliability groups to meet aggressive timelines while maintaining high quality standards.