Director of Power Package Design & Integration

Renesas; San Jose (CA); On-site; USD 230,000 - 260,000; Full time

Job summary

Renesas is seeking a senior-level engineer to lead package technology development, NPIs, and OSAT management for advanced power packaging solutions including Smart Power Stages and Discrete FETs.

The role emphasizes wafer-level, flip-chip packaging knowledge, DOE optimization, and close collaboration with product, Reliability, and operations teams to ensure timely ramp-to-production with high quality.

Qualifications

• Doctorate/Masters / Bachelor’s Degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.
• 15 to 20 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip packaging
• Strong understanding of power SiP/modules, wafer level/flip-chip packaging methods, assembly process knowledge, qualification methods, SPC and statistical analysis software

Responsibilities

• Lead package development, NPIs, and OSAT management for new package tech roadmap.
• Develop and qualify power SiP/module packaging, including SiC/GaN and interconnects.
• Coordinate with OSAT/CM, DOE, and production to ensure quality and on-time ramp.

Skills

Power SiP/Module knowledge

Wafer level packaging

Flip-chip packaging

Assembly process knowledge

SPC & statistical analysis

Interpersonal & communication

Education

Doctorate/Masters / Bachelor’s Degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering

Job description

Renesas is seeking a senior-level engineer to lead package technology development, NPIs, and OSAT management for advanced power packaging solutions including Smart Power Stages and Discrete FETs.

The role emphasizes wafer-level, flip-chip packaging knowledge, DOE optimization, and close collaboration with product, Reliability, and operations teams to ensure timely ramp-to-production with high quality.