Senior Power Packaging Design Lead

Renesas Electronics

Tempe (AZ)

On-site

USD 120,000 - 160,000

Full time

2 days ago

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Job summary

Renesas Electronics in Tempe, AZ is seeking an experienced packaging engineer to design and qualify power SiP/module packages, including wafer-level and flip-chip LGA concepts, and to work with OSAT/CM suppliers to drive robust production ready solutions.

You will lead DOE studies, establish process specs, and collaborate with Product, Reliability, Quality and Operations to ensure on-time ramp and superior quality.

Qualifications

10–15 years of experience in package development emphasizing power SiP/module packaging.
Experience with substrate or embedded die/capacitor packaging and assembly processes.
Strong knowledge of qualification methods, SPC and statistics.
Excellent interpersonal and communication skills.

Responsibilities

Design and develop package/interconnect methods for Renesas packaging needs (Power SiP/modules, flip-chip LGA, multi-chip/module with substrate).
Qualify materials, processes, and OSAT/CM providers; run DOEs to optimize processes and establish specs.
Collaborate with Product groups and Reliability to qualify new packages within required timelines.
Establish production controls and ensure smooth transition into production and ramp-up monitoring.

Skills

Power SiP/module packaging

Wafer level packaging

Flip-chip LGA packaging

DOE optimization

Statistical analysis

Production ramp-up

Education

Engineering degree (Physics/Chemical/Mechanical/Electrical/Materials)

Tools

Statistical analysis software

Cu FSM/BGBM knowledge

Job description

You will lead DOE studies, establish process specs, and collaborate with Product, Reliability, Quality and Operations to ensure on-time ramp and superior quality.

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