Senior Physical Design Lead – RTL to GDSII

Cisco Systems, Inc.; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco is seeking a seasoned Physical Design Engineer to drive end-to-end RTL-to-GDSII implementation for Silicon One optics, delivering first-pass silicon success on advanced nodes. You will own floorplanning, placement, and signoff while coordinating with RTL, Analog, DFT, and CAD teams across global sites.

You will architect scalable digital flows, automate using Python/TCL, and push QoR improvements while meeting tight schedules and quality targets.

Qualifications

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience.
• Experience in ASIC/SoC physical design and implementation in advanced tech nodes.
• Hands-on experience with the full physical design flow at block and/or chip level.
• Experience with EDA tool flows, back-end sign-off criteria, and workflow automation utilizing Python, TCL, and Shell scripts.

Responsibilities

• Full-Flow Ownership & First-Pass Tapeout: Lead end-to-end RTL-to-GDSII physical design implementation across advanced nodes, driving hierarchical floorplanning, complex mixed-signal macro placement, and signoff (STA, IR/EM, PV) to ensure first-pass silicon success.
• Methodology & Flow Innovation: Architect and scale digital implementation flows, leveraging custom TCL/Python automation and close EDA vendor partnerships to elevate QoR, optimize turnaround time, and improve team-wide productivity.
• Cross-Functional Design Convergence: Lead physical execution across PnR, CTS, MMMC timing closure, and ECO iterations, collaborating closely with RTL, Analog, DFT, Packaging, and CAD teams to resolve complex cross-domain bottlenecks.

Skills

ASIC/SoC design

Physical design flow

EDA tools

Python scripting

RTL to GDSII

Tools

Python

Job description

Cisco is seeking a seasoned Physical Design Engineer to drive end-to-end RTL-to-GDSII implementation for Silicon One optics, delivering first-pass silicon success on advanced nodes. You will own floorplanning, placement, and signoff while coordinating with RTL, Analog, DFT, and CAD teams across global sites.

You will architect scalable digital flows, automate using Python/TCL, and push QoR improvements while meeting tight schedules and quality targets.