Senior Physical Design Engineer – RTL-to-GDS & PPA

Intel Corporation; Hillsboro (OR); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health and retirement programs

Competitive vacation

Job summary

Intel Corporation seeks a Physical Design Engineer to drive RTL-to-GDS design convergence, perform floor planning, and optimize power, timing, and area across chip packages. You will partner with CAD teams to implement advanced design techniques and deliver silicon-ready layouts for cutting-edge technologies.

The role emphasizes collaboration on back-end flows, ECOs, and sign-off processes while leveraging AI tools to improve productivity and reliability.

Qualifications

• Bachelor's degree + 6+ years in physical design, or Master's + 4+ years
• weight? (not applicable)??

Responsibilities

• Drive RTL-to-GDS design convergence for performance, power, and area goals.
• 0
• Deliver block-level physical design and ensure backend closure.
• Collaborate with CAD and design teams to adopt leading tools for custom designs.
• Perform floor planning, bus/pin placement, power/clock distribution, timing closure, IR drop analysis, and physical verification.
• Debug timing, EM/IR, LVS, and DRC violations and drive sign-off for silicon production.
• Work with IP teams to optimize memory macros and standard cells.
• Develop and refine physical design methodologies to improve workflow and productivity.

Skills

RTL-to-GDS design

Floor planning

Timing constraints

Python scripting

FEV/RV analysis

ECOs

Chiplet integration

AI tooling

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in EE/CE (preferred)

Tools

Cadence Virtuoso

Synopsys Fusion Compiler

Job description

Intel Corporation seeks a Physical Design Engineer to drive RTL-to-GDS design convergence, perform floor planning, and optimize power, timing, and area across chip packages. You will partner with CAD teams to implement advanced design techniques and deliver silicon-ready layouts for cutting-edge technologies.

The role emphasizes collaboration on back-end flows, ECOs, and sign-off processes while leveraging AI tools to improve productivity and reliability.