ASIC Physical Design Engineer II - RTL-to-GDSII Innovator

Anysilicon; San Jose (CA); Hybride; USD 140 000 - 200 000; Plein temps

Résumé du poste

Cisco's Silicon One team seeks a highly motivated ASIC Physical Design Engineer II to drive RTL-to-GDSII implementation for sub-16nm to 3nm nodes. You will define floor plans, place-and-route, clock and power strategies, and ensure timing convergence across multi-mode/multi-corner designs.

Collaborating with RTL, DFT, and EDA vendors, you will develop automation scripts and push innovative timing methodologies, contributing to best practices and project-wide methodology alignment.

Qualifications

• Requires Master’s degree with 0 years or Bachelor’s with 2 years in ASIC Physical Design or related field.
• Foundational knowledge of physical design concepts including floor planning, clock tree synthesis, power distribution, I/O planning.
• Exposure to physical design lifecycle: synthesis, placement, routing, timing closure.

Responsabilités

• Own RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
• Define and execute floor planning, place & route, clock/power distribution, timing convergence strategies.
• Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; automate scripts in STA tools.

Connaissances

Python scripting

Tcl scripting

Perl scripting

Cadence Innovus

Synopsys ICC2

Synopsys Design Compiler

PrimeTime

Calibre DRC/LVS

Formation

Master's degree

Bachelor's degree

Outils

Mentor Calibre

Synopsys ICV

Cadence Innovus

Synopsys ICC2

Description du poste

Cisco's Silicon One team seeks a highly motivated ASIC Physical Design Engineer II to drive RTL-to-GDSII implementation for sub-16nm to 3nm nodes. You will define floor plans, place-and-route, clock and power strategies, and ensure timing convergence across multi-mode/multi-corner designs.

Collaborating with RTL, DFT, and EDA vendors, you will develop automation scripts and push innovative timing methodologies, contributing to best practices and project-wide methodology alignment.