Lead Physical Design Engineer - ASIC/SoC

Cisco Systems, Inc; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco Systems, Inc. in the U.S. seeks a Physical Design Engineer for Silicon One Optics to floorplan, tape out, and realize next-gen transceivers and driver ICs powering AI data centers.

You will own end-to-end RTL-to-GDSII physical design, drive hierarchical floorplanning, and collaborate with RTL, Analog, DFT, Packaging, and CAD teams, using Python/TCL/Shell automation to boost QoR and efficiency.

Qualifications

• Bachelors + 8 years of related experience or Masters + 6 years or PhD + 3 years.
• Prior experience in ASIC/SoC physical design and implementation in advanced tech nodes.
• Hands-on experience with full physical design flow at block and/or chip level.
• Experience with EDA tool flows, back-end sign-off criteria, and workflow automation using Python, TCL, and Shell scripts.

Responsibilities

• Full-Flow Ownership & First-Pass Tapeout: RTL-to-GDSII physical design across advanced nodes.
• Architect and scale digital implementation flows with TCL/Python automation.
• Lead cross-domain convergence with RTL, Analog, DFT, Packaging, and CAD teams.

Skills

ASIC/SoC physical design

RTL-to-GDSII

End-to-end physical design flow

Python/TCL/Shell scripting

Cross-functional collaboration

Education

Bachelor's degree or higher in relevant field

Master’s degree or PhD in related field

Tools

EDA tools

Python

TCL

Shell scripting

Job description

Cisco Systems, Inc. in the U.S. seeks a Physical Design Engineer for Silicon One Optics to floorplan, tape out, and realize next-gen transceivers and driver ICs powering AI data centers.

You will own end-to-end RTL-to-GDSII physical design, drive hierarchical floorplanning, and collaborate with RTL, Analog, DFT, Packaging, and CAD teams, using Python/TCL/Shell automation to boost QoR and efficiency.