ASIC Physical Design Engineer II — RTL-to-GDSII Expert

Cisco Systems, Inc; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Cisco Systems, Inc is seeking a Physical Design Engineer to lead RTL-to-GDSII implementation for advanced nodes and collaborate across RTL, DFT, and EDA teams. You will drive floor planning, place-and-route, clock/power distribution, and timing convergence to deliver high-performance networking chips.

Ideal candidates have hands-on experience with STA, timing closure, and scripting for automation, plus familiarity with Cadence Innovus, Synopsys ICC2, and Design Compiler.

Qualifications

• Master's degree in ASIC Physical Design or related field (completed within 3 years or soon).
• Bachelor's degree with 2 years of work experience in ASIC/physical design or related.
• Foundational knowledge of ASIC physical design and implementation flows.
• Understanding of floor planning, clock tree synthesis, power distribution, and I/O planning.
• Exposure to physical design lifecycle: synthesis, placement, routing, timing closure.

Responsibilities

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
• Define hierarchical floor planning, place-and-route, clock/power distribution, and timing convergence strategies.
• Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated STA scripts.
• Implement and manage timing ECO strategies using Tweaker/PrimeTime.
• Analyze quality gaps and propose tool/flow/methodology improvements.
• Collaborate with RTL, DFT, and EDA vendors to improve design efficiency.

Skills

Python

Tcl

Perl

STA

Education

Master's degree in ASIC Physical Design or related field

Bachelor's degree with 2 years of experience

Tools

Cadence Innovus

Synopsys ICC2

Synopsys Design Compiler

Mentor Calibre

Synopsys ICV

Job description

Cisco Systems, Inc is seeking a Physical Design Engineer to lead RTL-to-GDSII implementation for advanced nodes and collaborate across RTL, DFT, and EDA teams. You will drive floor planning, place-and-route, clock/power distribution, and timing convergence to deliver high-performance networking chips.

Ideal candidates have hands-on experience with STA, timing closure, and scripting for automation, plus familiarity with Cadence Innovus, Synopsys ICC2, and Design Compiler.