Senior ASIC Physical Design Architect

Cisco Systems, Inc; San Jose (CA); On-site; USD 251,000 - 363,000; Full time

Job summary

Cisco Systems, Inc is seeking a senior ASIC design engineer to lead fullchip floorplanning, collaborate with RTL, DFT, and EDA teams, and optimize clocking, power, and die size for cutting-edge hardware platforms. You will drive RTL-to-GDSII flow and sign-off readiness while coordinating with foundry partners and IP vendors.

You will implement hierarchical flows, analyze tool chains, apply UPF low-power techniques, and push AI-assisted design improvements through the entire physical design

Qualifications

• 15+ years of ASIC experience with a relevant engineering degree.
• Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
• Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.

Responsibilities

• Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
• Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
• Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Handson experience with Fullchip clock mesh and Flex-HTree methods
• RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
• Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
• Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.
• Proficiency in low-power design methodologies using UPF
• Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post-Silicon Validation teams
• Experience in using AI tools to improve productivity

Skills

Fullchip floorplan

RTL-to-GDSII

Clock mesh / H-Tree

AI tools usage

Education

Engineering degree with 15+ years ASIC experience

Tools

Innovus

Tempus

Primetime

Redhawk/Voltus

Calibre/Pegasus

Job description

Cisco Systems, Inc is seeking a senior ASIC design engineer to lead fullchip floorplanning, collaborate with RTL, DFT, and EDA teams, and optimize clocking, power, and die size for cutting-edge hardware platforms. You will drive RTL-to-GDSII flow and sign-off readiness while coordinating with foundry partners and IP vendors.

You will implement hierarchical flows, analyze tool chains, apply UPF low-power techniques, and push AI-assisted design improvements through the entire physical design