Senior ASIC Physical Design Lead - Fullchip & Optimization

Cisco Systems, Inc.; San Jose (CA); On-site; USD 214,000 - 310,000; Full time

Benefits offered by this job

Life insurance

Vision insurance

Parental leave

Paid holidays

Sick time

401(k)

Job summary

Cisco Systems, Inc. is seeking a Senior ASIC Physical Design Engineering Technical Lead to drive fullchip floorplanning and RTL-to-GDSII implementation for state-of-the-art silicon platforms.

You will collaborate with RTL, DFT, and EDA vendors to deliver high-performance, power-efficient chip layouts while advancing signoff methodologies with foundry partners. The role emphasizes cutting-edge flow optimizations and AI-assisted productivity in a fast-paced environment.

Qualifications

• Bachelor's Degree in Electrical Engineering; 12+ years PD experience or MS 8+ years or PhD 5+ years.
• Experience with RTL2GDSII flow and tapeouts in 7nm/5nm/3nm or below.
• Experience with EDA tools such as Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.

Responsibilities

• Fullchip Floorplan by architecture and IP constraints understanding.
• Collaborate with system and package design teams for requirements incorporation.
• Perform hierarchical implementation flow: partition, pin assignment, clock plan, bump planning.
• RTL-to-GDSII: Floorplan, Power Grid, place and route, timing analysis, PVT and EV checks.
• Analyze tool flows to improve efficiency and implement enhancements.
• Work with RTL, DFT, EDA vendors and tool teams to enable design methodologies.
• Proficiency in low-power design using UPF.
• Define signoff methodologies with foundry/IP vendors and adjust with feedback from Post-Silicon Validation.
• Experience using AI tools to improve productivity.

Skills

RTL2GDSII flow

7nm/5nm/3nm tech

EDA tools

Fullchip floorplan

Hierarchical design

Timing closure

Python

AI tools prompts

Education

Bachelor's Degree in Electrical Engineering

Master's Degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Innovus

Tempo/Primetime

Redhawk/Voltus

Calibre/Pegasus

Job description

Cisco Systems, Inc. is seeking a Senior ASIC Physical Design Engineering Technical Lead to drive fullchip floorplanning and RTL-to-GDSII implementation for state-of-the-art silicon platforms.

You will collaborate with RTL, DFT, and EDA vendors to deliver high-performance, power-efficient chip layouts while advancing signoff methodologies with foundry partners. The role emphasizes cutting-edge flow optimizations and AI-assisted productivity in a fast-paced environment.