ASIC Physical Design Engineer II: RTL-to-GDSII Specialist

Cisco; San Jose (CA); On-site; USD 126,000 - 203,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) with Cisco matching

Paid parental leave

Job summary

Cisco’s Silicon One team is seeking a Physical Design Engineer to lead RTL-to-GDSII implementation for cutting-edge Networking chips. You will optimize floor planning, timing, and backend flows while collaborating across RTL, DFT, and EDA teams to secure high-performance silicon.

The role requires expertise in ASIC physical design concepts, floor planning, clock and power distribution, and STA. Proficiency with Cadence Innovus, Synopsys tools, and scripting is highly valued.

Qualifications

• Qualifying education in ASIC Physical Design or related field.
• Strong knowledge of floor planning, clock tree synthesis, and power distribution.
• Experience with RTL-to-GDSII flows and timing closure.

Responsibilities

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
• Define and execute hierarchical floor planning, place and route, clock/power distribution, timing convergence.
• Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; develop scripts in STA tools.
• Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime.
• Collaborate with RTL, DFT, EDA vendors and tool owners to improve design efficiency.

Skills

RTL-to-GDSII implementation

Floor planning

Static timing analysis (STA)

Python scripting

Collaboration

Education

Master's degree in Electrical Engineering or related field

Bachelor's degree in Electrical Engineering or related field

Tools

Cadence Innovus

Synopsys ICC2

Synopsys Design Compiler

Mentor Calibre

PrimeTime

Job description

Cisco’s Silicon One team is seeking a Physical Design Engineer to lead RTL-to-GDSII implementation for cutting-edge Networking chips. You will optimize floor planning, timing, and backend flows while collaborating across RTL, DFT, and EDA teams to secure high-performance silicon.

The role requires expertise in ASIC physical design concepts, floor planning, clock and power distribution, and STA. Proficiency with Cadence Innovus, Synopsys tools, and scripting is highly valued.