Advanced ASIC Physical Design Engineer

Cisco Systems, Inc.; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Medical, dental & vision insurance

401(k) with company match

Paid parental leave

Disability coverage

Life insurance

Bonus potential

Restricted stock units

Job summary

Cisco Systems, Inc. is seeking a Physical Design Engineer in the Silicon One team to lead RTL-to-GDSII implementation for cutting-edge nodes. You will define floor planning, place-and-route, clock/power distribution, and timing convergence while collaborating with RTL, DFT, and EDA vendors across multiple projects.

The role requires hands-on experience with STA, timing closure, and scripting for automation. A strong foundation in ASIC flows and tools like PrimeTime is essential.

Qualifications

• Master's degree in ASIC Physical Design, or related field with 0 years of work experience or
• Bachelor's degree with 2 years of work experience in ASIC physical design or related field
• Foundational knowledge of ASIC physical design and implementation flows
• Understanding of floor planning, clock tree synthesis, power distribution, and I/O planning
• Exposure to physical design lifecycle: synthesis, placement, routing, and timing closure

Responsibilities

• Own RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm)
• Define hierarchical floor planning, place and route, clock and power strategies
• Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; develop scripts
• Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime
• Analyse gaps and suggest tool/flow/methodology improvements
• Collaborate with RTL, DFT, EDA vendors, and tool owners to improve efficiency
• Contribute to best practices and align methodologies across projects

Skills

Python

Tcl

Perl

Education

Master's degree

Bachelor's degree with 2 years

Tools

Cadence Innovus

Synopsys ICC2

Synopsys Design Compiler

Mentor Calibre

PrimeTime

ICV

Job description

Cisco Systems, Inc. is seeking a Physical Design Engineer in the Silicon One team to lead RTL-to-GDSII implementation for cutting-edge nodes. You will define floor planning, place-and-route, clock/power distribution, and timing convergence while collaborating with RTL, DFT, and EDA vendors across multiple projects.

The role requires hands-on experience with STA, timing closure, and scripting for automation. A strong foundation in ASIC flows and tools like PrimeTime is essential.