Senior Physical Design Lead for AI ASICs (TPU)

Google LLC; Sunnyvale (CA); Vor Ort; USD 192.000 - 278.000; Vollzeit

Zusammenfassung

Google LLC in Sunnyvale, CA seeks a Physical Design Technical Lead for ASIC TPUs to drive end-to-end implementation from RTL to GDSII. You will lead floorplanning, placement, routing, and timing closure for high-speed ASICs, across multiple process nodes.

You will collaborate with RTL, DFT, methodology, and packaging teams to achieve optimal power, performance, and area, while managing schedules and risks and guiding cross-functional execution.

Qualifikationen

• Bachelor's degree or equivalent practical experience.
• 10 years in physical design, leading full-chip or sub-chip implementation; RTL2GDSII; floorplanning, place & route, timing closure for high-speed ASICs across nodes.
• Experience in Python, Tcl, or Perl scripting.

Aufgaben

• Lead the physical design implementation and strategy for high-performance silicon, from subchips to top-level execution based on project needs.
• Manage full design cycle from RTL to GDSII, including sign-off closures for timing, electrical performance, and power integrity.
• Partner with RTL, DFT, methodology, packaging teams to optimize PPA and run feasibility studies for new microarchitectures; drive RTL runs.
• Collaborate with external EDA and IP vendors to improve flows and methodologies; contribute to internal processes for efficient execution.
• Drive execution schedules, resource planning, and risk mitigation across your ownership area; scale leadership to project milestones.

Kenntnisse

Physical design leadership

RTL to GDSII

Floorplanning

Place & route

Timing closure

Python scripting

Tcl scripting

Perl scripting

Ausbildung

Bachelor's degree in Electrical/Computer Engineering or related field

Equivalent practical experience

Tools

Cadence Innovus

Synopsys DP

Mentor Calibre

StarRC

Jobbeschreibung

Google LLC in Sunnyvale, CA seeks a Physical Design Technical Lead for ASIC TPUs to drive end-to-end implementation from RTL to GDSII. You will lead floorplanning, placement, routing, and timing closure for high-speed ASICs, across multiple process nodes.

You will collaborate with RTL, DFT, methodology, and packaging teams to achieve optimal power, performance, and area, while managing schedules and risks and guiding cross-functional execution.