TPU Physical Design Lead for AI Accelerators

Google LLC; Sunnyvale (CA); Vor Ort; USD 192.000 - 278.000; Vollzeit

Zusammenfassung

Google LLC in Sunnyvale, CA is seeking a senior IC design engineer to shape the future of AI/ML hardware acceleration. You will own custom datapath blocks and drive RTL-to-GDSII through synthesis, floorplanning, PNR, timing, and signoff, advancing TPU architecture.

Partner with teams to optimize PPA for dense datapaths on sub-7nm nodes, mentor a small engineering group, and contribute to Google's AI infrastructure with cutting-edge silicon solutions.

Qualifikationen

• Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, or related field.
• 10 years of experience in physical design, including custom structured datapath implementation.
• Experience hardening dense compute units into high-frequency, low-power macros.
• Experience in sub-7nm process nodes (FinFET and Gate-All-Around), managing the physical density and routing congestion typical of custom datapaths.

Aufgaben

• Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL-to-GDSII including synthesis, floor-planning, place and route (PNR), timing closure, and physical signoff.
• Understand math-intensive micro-architecture to perform detailed feasibility studies, analyzing performance, power, and area (PPA) tradeoffs to achieve optimal design closure.
• Develop and improve advanced physical design methodologies and customize implementation recipes, specifically optimizing PPA across complex arithmetic pipeline structures. Manage different PNR tools - Synopsys Fusion Compiler, Cadence Innovus/Genus, PrimeTime, StarRC, Calibre, Apache Redhawk.
• Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (DRC/LVS, EM/IR), and final signoff.
• Lead sub-chip execution and drive delivery, providing direct technical guidance and mentorship to a small team of engineers to ensure on-schedule project completion.

Kenntnisse

10 years of experience in physical设计

Experience in hardening dense compute-

Experience in sub-7nm process nodes

Ausbildung

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Synopsys Fusion Compiler

Cadence Innovus

Cadence Genus

Synopsys PrimeTime

StarRC

Calibre

Apache RedHawk

Jobbeschreibung

Google LLC in Sunnyvale, CA is seeking a senior IC design engineer to shape the future of AI/ML hardware acceleration. You will own custom datapath blocks and drive RTL-to-GDSII through synthesis, floorplanning, PNR, timing, and signoff, advancing TPU architecture.

Partner with teams to optimize PPA for dense datapaths on sub-7nm nodes, mentor a small engineering group, and contribute to Google's AI infrastructure with cutting-edge silicon solutions.