3D Physical Design Engineer – AI/TPU ASICs

Google LLC; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google LLC in Sunnyvale, CA, is seeking a Physical Design Engineer, 3D Technology, to shape the future of AI/ML hardware acceleration. You will contribute to TPU architecture and integration within AI/ML systems, partnering with PD, circuit design, and architecture teams to drive cutting-edge ASIC/SoC outcomes.

The role emphasizes 3D physical design flows, TSV-based methodology and verification, and performance optimization across blocks, clocking, and IP integration, with a focus on high‑end

Qualifications

• Bachelor's degree or equivalent practical experience.
• 4 years of experience with physical design and 3D integration technologies.
• Experience running industry standard chip-design tools (Synopsys, Cadence, Siemens EDA/Mentor Graphics).

Responsibilities

• Drive development of a leading edge 3D technology platform for ASICs and SoCs from design to tapeout.
• Optimize digital blocks for performance, power, area, and reliability using PD and circuit techniques.
• Define methodologies by investigating performance, power, and area across different technology nodes and implementation techniques.
• Collaborate with PD, technology, circuits, and IP partners in advanced CMOS nodes.
• Design and build custom circuits at transistor and gate levels to support layout optimization.

Skills

Chip design experience

3D integration

EDA tools proficiency

Education

Bachelor's degree in Electrical Engineering / Computer Engineering / Computer Science or related field

Tools

Synopsys

Cadence

Siemens EDA / Mentor Graphics

Job description

Google LLC in Sunnyvale, CA, is seeking a Physical Design Engineer, 3D Technology, to shape the future of AI/ML hardware acceleration. You will contribute to TPU architecture and integration within AI/ML systems, partnering with PD, circuit design, and architecture teams to drive cutting-edge ASIC/SoC outcomes.

The role emphasizes 3D physical design flows, TSV-based methodology and verification, and performance optimization across blocks, clocking, and IP integration, with a focus on high‑end