TPU RTL Design Engineer – AI Hardware Acceleration

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google LLC in Sunnyvale, CA, is seeking an experienced RTL design engineer to help shape the future of AI/ML hardware acceleration and TPU technology for data center workloads. You will contribute to cutting-edge silicon solutions powering Google's AI capabilities and collaborate across software, hardware, and architecture teams to deliver robust RTL designs and verification.

The role focuses on SoC-level RTL design for TPU-related accelerators, developing IP for management and control

Qualifications

• Bachelor's degree or equivalent practical experience.
• Experience with scripting languages.
• Strong collaboration across software and hardware teams.

Responsibilities

• Design RTL IP with focus on management and control subsystem.
• Develop SystemVerilog RTL for ASIC products per guidelines.
• Coordinate with architecture and power teams to assess features.

Skills

Scripting languages

ASIC design

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science with emphasis on computer architecture

Tools

SystemVerilog

Interface protocols (I2C, SPI, UART)

Job description

Google LLC in Sunnyvale, CA, is seeking an experienced RTL design engineer to help shape the future of AI/ML hardware acceleration and TPU technology for data center workloads. You will contribute to cutting-edge silicon solutions powering Google's AI capabilities and collaborate across software, hardware, and architecture teams to deliver robust RTL designs and verification.

The role focuses on SoC-level RTL design for TPU-related accelerators, developing IP for management and control