Senior ASIC PD Engineer for TPU AI Hardware

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google LLC in Sunnyvale, CA, USA seeks a Share Senior ASIC Physical Design Engineer to drive the PD of TPU blocks from RTL to GDSII. You will collaborate with RTL, DFT, floorplanning, and full-chip signoff teams to optimize power, performance, and area while evaluating new micro-architectures and practical logic solutions.

The role requires working closely with external partners on PD closure and understanding STA, timing corners, derates, and PnR flows using Synopsys/Cadence tools.

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• 7 years of experience with physical design from RTL to GDSII, including floorplanning, place & route, timing closure.
• Experience in Python, Tcl, or Perl scripting.

Responsibilities

• Participate in the physical design of complex blocks and full-chip integration from RTL to GDSII.
• Collaborate with RTL, DFT, Floorplan, and Signoff teams to optimize PPA.
• Work with internal/external teams to achieve PD closure and timing objectives.

Skills

Physical design

Scripting (Python/Tcl/Perl)

RTL-to-GDSII knowledge

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

Synopsys/Cadence PnR tools

Backend flows: DRC/LVS/PI/SI/LEC

DFT: Scan/MBIST/LBIST

Job description

Google LLC in Sunnyvale, CA, USA seeks a Share Senior ASIC Physical Design Engineer to drive the PD of TPU blocks from RTL to GDSII. You will collaborate with RTL, DFT, floorplanning, and full-chip signoff teams to optimize power, performance, and area while evaluating new micro-architectures and practical logic solutions.

The role requires working closely with external partners on PD closure and understanding STA, timing corners, derates, and PnR flows using Synopsys/Cadence tools.