Physical Design Lead, TPU, ASIC

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google is hiring for a leadership role in AI/ML hardware acceleration, focusing on TPU architecture and its integration within AI-driven systems. You will drive the physical design of critical sub-chips on the next-generation AI silicon, leading cross-functional teams and coordinating with RTL, DFT, and packaging groups to ensure scalable, high-performance designs.

The role emphasizes collaboration with internal teams and external vendors to optimize power, performance, and area while navigating

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 10 years of experience in physical design, including leading full-chip or sub-chip implementation such as RTL2GDSII and overseeing key stages like floorplanning, place and route, and timing closure for high-speed ASICs across various process nodes.
• Experience in Python, Tcl, or Perl scripting.

Responsibilities

• Lead the physical design implementation and strategy for high-performance silicon for critical, high-complexity subchips.
• Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
• Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
• Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
• Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.

Skills

Physical design experience

Scripting (Python/Tcl/Perl)

Leadership in ASIC projects

Education

Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science

Tools

Cadence Innovus

Synopsys DP

Mentor Calibre

StarRC

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in physical design, including leading full-chip or sub-chip implementation such as RTL2GDSII and overseeing key stages like floorplanning, place and route, and timing closure for high-speed ASICs across various process nodes.
• Experience in Python, Tcl, or Perl scripting.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, and understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
• Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
• Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
• Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.

About The Job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will work and provide technical leadership for the physical design of critical sub-chips on our next-generation AI silicon. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We’re the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits.

Responsibilities

Learn more about benefits at Google .

• Lead the physical design implementation and strategy for high-performance silicon for critical, high-complexity subchips.
• Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
• Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
• Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
• Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .