TPU ASIC Physical Design Lead — Shape AI Hardware

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google is hiring for a leadership role in AI/ML hardware acceleration, focusing on TPU architecture and its integration within AI-driven systems. You will drive the physical design of critical sub-chips on the next-generation AI silicon, leading cross-functional teams and coordinating with RTL, DFT, and packaging groups to ensure scalable, high-performance designs.

The role emphasizes collaboration with internal teams and external vendors to optimize power, performance, and area while navigating

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 10 years of experience in physical design, including leading full-chip or sub-chip implementation such as RTL2GDSII and overseeing key stages like floorplanning, place and route, and timing closure for high-speed ASICs across various process nodes.
• Experience in Python, Tcl, or Perl scripting.

Responsibilities

• Lead the physical design implementation and strategy for high-performance silicon for critical, high-complexity subchips.
• Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
• Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
• Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
• Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.

Skills

Physical design experience

Scripting (Python/Tcl/Perl)

Leadership in ASIC projects

Education

Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science

Tools

Cadence Innovus

Synopsys DP

Mentor Calibre

StarRC

Job description

Google is hiring for a leadership role in AI/ML hardware acceleration, focusing on TPU architecture and its integration within AI-driven systems. You will drive the physical design of critical sub-chips on the next-generation AI silicon, leading cross-functional teams and coordinating with RTL, DFT, and packaging groups to ensure scalable, high-performance designs.

The role emphasizes collaboration with internal teams and external vendors to optimize power, performance, and area while navigating