Senior PCS/PMA RTL Design Engineer - High-Speed Interconnects

Astera Labs; San Jose (CA); On-site; USD 185,000 - 240,000; Full time

Job summary

Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focusing on PCS and PMA logic for high-speed interconnects such as Ethernet, PCIe, UCIe, and UALink. You will translate microarchitectural specs into synthesizable RTL and collaborate with SerDes/verification, physical design, and firmware teams.

You will work on clock/data recovery, equalization, calibration, and multi-lane design, delivering robust designs through tapeout and silicon validation.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering required.
• 3+ years of relevant experience in digital ASIC/SoC/RTL design.
• Hands-on experience with Verilog or SystemVerilog RTL development and RTL debugging.

Responsibilities

• PCS/PMA RTL design and implementation for Ethernet, PCIe, UCIe, and UALink.
• Implement PCS functions: encoding/decoding, scrambling, alignment, deskew, lane reordering, gearboxes, FIFOs, rate adaptation.
• Implement forward error correction (RS-FEC/KP4, FEC framing, interleaving) and related control logic.
• Design PMA digital interface logic, including SerDes datapaths, CDR interfaces, and link-training control.
• Develop lane-level and multi-lane logic, including PRBS, loopback, and BIST features.
• Translate architectures into datapaths, control, state machines, and protocol logic; create reusable RTL modules.
• Integrate internal/third-party IP and follow established design methodologies.
• Support RTL reviews, lint, CDC/RDC checks, and multi-clock-domain considerations.
• Collaborate with verification and backend teams to ensure timing, power, and area goals.

Skills

RTL design

Verilog/SystemVerilog

High-speed protocols

Digital ASIC/SoC

Collaboration

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree preferred

Tools

Cadence Genus/Innovus

Synopsys Design Compiler/ICC2

Verilog tooling

Job description

Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focusing on PCS and PMA logic for high-speed interconnects such as Ethernet, PCIe, UCIe, and UALink. You will translate microarchitectural specs into synthesizable RTL and collaborate with SerDes/verification, physical design, and firmware teams.

You will work on clock/data recovery, equalization, calibration, and multi-lane design, delivering robust designs through tapeout and silicon validation.