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Astera Labs in the United States is seeking a Principal Digital Design Engineer to lead front-end circuit design, RTL, synthesis, IP integration, and block-level verification for high-performance network controllers. You will own the front-end from architecture to GDS and drive complex designs to production.
The ideal candidate has deep experience with PCIe, Ualink, Esun, Ethernet, UVM-based verification, and 8+ years in SoC/silicon products. US work authorization is required.
Astera Labs in the United States is seeking a Principal Digital Design Engineer to lead front-end circuit design, RTL, synthesis, IP integration, and block-level verification for high-performance network controllers. You will own the front-end from architecture to GDS and drive complex designs to production.
The ideal candidate has deep experience with PCIe, Ualink, Esun, Ethernet, UVM-based verification, and 8+ years in SoC/silicon products. US work authorization is required.