Principal Front-End Digital Design Engineer - PCIe/NVLink

Hardware FYI

San Jose (CA)

On-site

USD 185,000 - 230,000

Full time

3 days ago
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Job summary

Astera Labs in the United States is seeking a Principal Digital Design Engineer to lead front-end circuit design, RTL, synthesis, IP integration, and block-level verification for high-performance network controllers. You will own the front-end from architecture to GDS and drive complex designs to production.

The ideal candidate has deep experience with PCIe, Ualink, Esun, Ethernet, UVM-based verification, and 8+ years in SoC/silicon products. US work authorization is required.

Qualifications

  • Bachelor’s degree in EE; Master’s degree preferred.
  • 8+ years experience in SoC/silicon products for Switch ASIC or Networking/Server/Storage.
  • Professional attitude with the ability to prioritize multiple tasks and work with minimal supervision.
  • Authorized to work in the US and start immediately.

Responsibilities

  • Own front-end design from architecture to GDS and drive complex designs to production.
  • Implement RTL, simulations, synthesis, timing closure, DFT, GLS, and block-level verification.
  • Integrate IP and verify at block level; ensure interfaces and timing meet requirements.
  • Collaborate with cross-functional teams and customers to deliver production-ready designs.

Skills

RTL design
High-speed protocols
Front-end ownership
DFT/GLS/Testing
UVM verification
CMOS design

Education

Bachelor's degree in EE
Master's degree preferred

Tools

Synopsys tools
Cadence tools

Job description

Astera Labs in the United States is seeking a Principal Digital Design Engineer to lead front-end circuit design, RTL, synthesis, IP integration, and block-level verification for high-performance network controllers. You will own the front-end from architecture to GDS and drive complex designs to production.

The ideal candidate has deep experience with PCIe, Ualink, Esun, Ethernet, UVM-based verification, and 8+ years in SoC/silicon products. US work authorization is required.

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