Technical Lead, High-Speed Digital IC Design

Astera Labs; San Jose (CA); Vor Ort; USD 160.000 - 200.000; Vollzeit

Zusammenfassung

Astera Labs in San Jose, CA is seeking a Technical Lead Digital Design Engineer to drive RTL implementation of complex SoC blocks. You will work from micro-architecture through silicon bring-up, partnering with verification, PD and DFT teams to deliver high-performance connectivity solutions.

You’ll apply SystemVerilog, Python scripting, and upstream design flows with Synopsys/Cadence toolchains, ensuring timing closure and robust DFT features while mentoring junior engineers in a fast-paced,

Qualifikationen

• Bachelor’s degree in electrical engineering or equivalent.
• 5+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets.
• Expertise in RTL coding with SystemVerilog and synthesis.
• Experience in high-speed design in advanced technology nodes.
• Understanding of clocking, CDC and RDC and static-timing analysis.

Aufgaben

• Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
• Collaborate with verification teams to review test plans and debug issues.
• Support efforts to achieve timing closure and implement DFT features.
• Scripting and automation for ASIC methodology improvement.
• Accountable for quality and overall design success with the support of senior engineers.

Kenntnisse

RTL design

SystemVerilog

Python

High-speed design

Clocking/CDC/RDC

STA

Cross-functional collaboration

Ausbildung

Bachelors in Electrical Engineering

Tools

Synopsys tools

Cadence tools

UVM basics

Jobbeschreibung

Astera Labs in San Jose, CA is seeking a Technical Lead Digital Design Engineer to drive RTL implementation of complex SoC blocks. You will work from micro-architecture through silicon bring-up, partnering with verification, PD and DFT teams to deliver high-performance connectivity solutions.

You’ll apply SystemVerilog, Python scripting, and upstream design flows with Synopsys/Cadence toolchains, ensuring timing closure and robust DFT features while mentoring junior engineers in a fast-paced,