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Astera Labs is seeking Principal Digital Design Engineers in the United States to lead front-end circuit design for high-performance network controllers. You will work on RTL, synthesis, IP integration, and block-level verification across PCIe, Ualink, Esun, and Ethernet protocols.
Qualifications include a Bachelor's in EE (Master's preferred), 8+ years in SoC/silicon for networking, and expertise with Synopsys/Cadence flows. US work authorization and immediate availability are required.
Astera Labs is seeking Principal Digital Design Engineers in the United States to lead front-end circuit design for high-performance network controllers. You will work on RTL, synthesis, IP integration, and block-level verification across PCIe, Ualink, Esun, and Ethernet protocols.
Qualifications include a Bachelor's in EE (Master's preferred), 8+ years in SoC/silicon for networking, and expertise with Synopsys/Cadence flows. US work authorization and immediate availability are required.