Principal Design Engineer — High-Speed Interconnect RTL

Arm; Austin (TX); Hybrid; USD 249,900 - 338,100; Full time

Job summary

Arm seeks a seasoned silicon engineer to own microarchitecture, RTL development, and integration of high-speed interconnect subsystems across multiple silicon products. You will translate system requirements into detailed RTL, interfaces, and register definitions, ensuring timely delivery.

You will drive the development process from concept to synthesis, collaborating with architecture, verification, performance, firmware, physical design, and implementation teams to meet bandwidth, latency,

Qualifications

• 8+ years in RTL, microarchitecture, or related semiconductor roles.
• Deep hands-on SystemVerilog for high-performance subsystems.
• Expertise in PCIe, CXL, UALink including transaction flows and memory connectivity.
• Experience with coherent/non-coherent interconnects and memory systems.
• Strong knowledge of AXI, CHI, ACE, APB, and streaming interfaces.
• Experience with CDC, RDC, reset sequencing, lint, formal verification, timing, and waveform debugging.
• Ability to translate architecture into microarchitecture docs and RTL.
• Proven leadership and cross-functional delivery.
• Bachelor’s or Master’s degree in EE/CE/CS or related.

Responsibilities

• Own microarchitecture, RTL development, and integration of high-speed interconnect subsystems.
• Translate requirements into microarchitecture specs, interfaces, register definitions, and RTL.
• Drive development from concept through RTL, integration, verification, and delivery.
• Collaborate with architecture, verification, performance, firmware, and design teams to meet targets.
• Analyze traffic, workloads, and buffer requirements to guide tradeoffs; lead technical reviews.

Skills

RTL design & microarchitecture

SystemVerilog

PCIe/CXL/UALink expertise

Coherent interconnects & memory

AXI/CHI/ACE interfaces

CDC/RDC/verification tooling

Technical leadership & delivery

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering/CS

Tools

PCIe

CXL

UALink

Synthesis

Formal verification

Job description

Arm seeks a seasoned silicon engineer to own microarchitecture, RTL development, and integration of high-speed interconnect subsystems across multiple silicon products. You will translate system requirements into detailed RTL, interfaces, and register definitions, ensuring timely delivery.

You will drive the development process from concept to synthesis, collaborating with architecture, verification, performance, firmware, physical design, and implementation teams to meet bandwidth, latency,