Senior Digital Design Manager - High-Speed AI Silicon

Astera Labs; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Flexible time off (US)

Parental leave

401K

Retirement plans

Medical, dental, and vision plans

Job summary

Astera Labs is seeking a Senior Manager/Manager, Digital Design to lead front-end RTL for high-performance PCIe & CXL, UAL, and ethernet devices. You will guide architecture through RTL development, verification, physical design, tape-out, and shipment, ensuring schedules and quality targets are met.

You will mentor 6–8 engineers, establish design checklists, and collaborate with architecture and system teams to translate requirements into robust digital implementations.

Qualifications

• Lead front-end RTL and digital design from requirements through tape-out.
• Drive two complex devices with milestones, decisions, risk tracking, and schedule accountability.
• Mentor a team of 6–8 digital design engineers.
• Define design checklists, gates, and signoff criteria.
• Work with PCIe/CXL/UAL/ethernet requirements to deliver robust designs.

Responsibilities

• Lead digital design execution from requirements through tape-out and production shipment.
• Ensure efficient synthesis, timing closure, and smooth tape-out with cross-functional teams.
• Communicate technical status, tradeoffs, and mitigation plans to engineering leadership.
• Develop scalable design practices and enforce coding standards across the lifecycle.

Skills

RTL development

Front-end digital design

Mentoring

Team leadership

Synthesis and timing

Design verification

Architecture collaboration

Signoff readiness

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Master’s or PhD in Electrical Engineering or Computer Engineering

Tools

Lint

Job description

Astera Labs is seeking a Senior Manager/Manager, Digital Design to lead front-end RTL for high-performance PCIe & CXL, UAL, and ethernet devices. You will guide architecture through RTL development, verification, physical design, tape-out, and shipment, ensuring schedules and quality targets are met.

You will mentor 6–8 engineers, establish design checklists, and collaborate with architecture and system teams to translate requirements into robust digital implementations.