Lead SerDes Bring-Up & Validation Engineer

Astera Labs; San Jose, Northern (CA, KY); Hybrid; USD 185,000 - 240,000; Full time

Job summary

Astera Labs, based in San Jose, CA, seeks a Principal SerDes Bring-up Validation Engineer to lead end-to-end post-silicon bring-up, validation, and characterization for high-speed PHYs. You will build automation, collaborate across AMS design, firmware, and system teams, and drive data-driven optimization of performance and reliability.

You will design and execute bring-up plans, develop test objectives and pass/fail criteria, and mentor across disciplines to accelerate time-to-data and improve

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 8-12 years of hands-on experience in mixed-signal, high-speed lab environments with industry instruments such as protocol analyzers, BERTs, real-time oscilloscopes, sampling scopes, TDRs, and VNAs.
• Proven track record in post-silicon validation and bring-up of high-speed PHYs or retimers, with a strong understanding of the physical layer and experience developing characterization flows and validating silicon against specifications.
• Deep understanding of NRZ and PAM4 architectures and high-speed building blocks (PLLs, CTLE, DFE, FFE, transmitter equalization).
• Practical experience bringing up and debugging retimers, including equalization tuning and reset/link sequencing.
• Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction.

Responsibilities

• Own end-to-end post-silicon bring up and characterization strategies, translating design/product requirements into measurable test objectives, pass/fail criteria, and schedules.
• Participate in architecture and design-spec reviews to ensure testability and trace requirements to verification plans.
• Perform silicon block level bring-up, functional and parametric testing, interop checks, and performance benchmarking; iterate on test flows.
• Develop scalable test automation, data capture, and analysis pipelines to increase throughput and coverage.
• Diagnose complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers; propose corrective actions.
• Trace issues to circuit, package, firmware, or protocol interactions and coordinate fixes with design teams.
• Collaborate with mixed-signal design, firmware, system engineering, and manufacturing to deliver results and validation reports.
• Produce clear debug reports, characterization summaries, and recommendations for design/process improvements.
• Write Python test scripts and control interfaces to configure and monitor multiple DSP/hardware platforms.
• Define validation metrics, track coverage and defect trends, and present data-driven conclusions to influence product direction.

Skills

Python

C/C++

Test automation

Post-silicon bring-up

High-speed PHYs

Debugging

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

MS or PhD in Electrical Engineering or related field

Tools

BERTs

VNAs

Oscilloscopes

Sampling scopes

TDRs

Job description

Astera Labs, based in San Jose, CA, seeks a Principal SerDes Bring-up Validation Engineer to lead end-to-end post-silicon bring-up, validation, and characterization for high-speed PHYs. You will build automation, collaborate across AMS design, firmware, and system teams, and drive data-driven optimization of performance and reliability.

You will design and execute bring-up plans, develop test objectives and pass/fail criteria, and mentor across disciplines to accelerate time-to-data and improve