Senior Digital Design Engineer: Front-End SoC for High-Speed Networks

Astera Labs; San Jose (CA); On-site; USD 140,000 - 230,000; Full time

Job summary

Astera Labs in San Jose, CA, seeks Senior Digital Design Engineers to advance front-end circuit design for high-performance network controllers. You will drive RTL, synthesis, IP integration, and block-level verification across PCIe, Ethernet, UALink, and related protocols.

The role requires a strong EE background with a Bachelor's, 3+ years of SoC experience, and hands-on design using Synopsys/Cadence flows. US work authorization is required.

Qualifications

• Bachelor's in EE required; Master's preferred.
• +3 years' experience with SoC/silicon products for networking/server storage.
• Strong RTL, synthesis, timing, and verification skills.
• End-to-end ownership from architecture to GDS.
• Experience with Synopsys/Cadence tool flows.
• DFT, UVM, silicon bring-up experience.
• Familiarity with PCIe, Ethernet, Ualink, Esun.

Responsibilities

• Develop front-end circuit design for high-performance network controllers.
• RTL development, synthesis, IP integration, and block-level verification.
• Lead timing closure and DFT, plus GDS flow ownership.
• Collaborate on PCIe, Ethernet, UALink, and related protocols.
• Bring-up and debug silicon; support for design verification.

Skills

RTL design

UVM verification

PCIe

Ethernet

Ualink

Esun

Scripting Python

DFT

Timing closure

GDS flow

Cadence/Synopsys tools

Silicon bring-up

Education

Bachelor's degree in EE

Master's degree preferred

Tools

Synopsys tools

Cadence tools

Job description

Astera Labs in San Jose, CA, seeks Senior Digital Design Engineers to advance front-end circuit design for high-performance network controllers. You will drive RTL, synthesis, IP integration, and block-level verification across PCIe, Ethernet, UALink, and related protocols.

The role requires a strong EE background with a Bachelor's, 3+ years of SoC experience, and hands-on design using Synopsys/Cadence flows. US work authorization is required.