Tech Lead Design Engineer - RTL & Silicon Architect

Astera Labs; San Jose (CA); On-site; USD 133,000 - 185,000; Full time

Job summary

Astera Labs in San Jose is seeking a Tech Lead Design Engineer to architect and deliver the connectivity silicon powering AI clusters. You will own RTL design for blocks from microarchitecture through tapeout and work at the cutting edge of PCIe, CXL, Ethernet, and UALink technologies.

This high-impact role partners with architecture, verification, DFT and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of digital design experience, including at least one full chip from spec to tapeout.
• Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows.
• Hands-on experience with timing closure, CDC, lint, and low-power design techniques.
• Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration.

Responsibilities

• Own RTL design for blocks from microarchitecture through synthesis sign-off.
• Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA.
• Drive design reviews, lint, CDC, and timing closure to silicon-ready quality.
• Partner with architecture to translate specifications into implementation-ready microarchitecture.
• Collaborate with verification on testplans, coverage closure, and bug triage.
• Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure.
• Mentor junior engineers and contribute to design methodology, scripts, and best practices.
• Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments.
• Drive structured, data-driven design decisions in support of aggressive tapeout schedules.

Skills

Verilog/SystemVerilog

RTL coding

Synthesis flows

Timing closure

CDC

Lint

Low-power design

High-speed interfaces

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

PCIe Gen5/Gen6

CXL

UALink

Ethernet MAC/PCS designs

Job description

Astera Labs in San Jose is seeking a Tech Lead Design Engineer to architect and deliver the connectivity silicon powering AI clusters. You will own RTL design for blocks from microarchitecture through tapeout and work at the cutting edge of PCIe, CXL, Ethernet, and UALink technologies.

This high-impact role partners with architecture, verification, DFT and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap.