Senior Packaging SIPI Engineer & System Lead

Qualcomm; San Diego (CA); On-site; USD 180,400 - 270,600; Full time

Job summary

The Qualcomm Package Electrical Team has an opening in signal integrity and power integrity. The candidate will work with package and IC designers to optimize the overall package design and perform system simulation to ensure all system level constraints are met prior to the package Tape-out.

The candidate is expected to communicate with PHY owners to understand IP specs and with PCB designers to assess the impact of ball assignment on system performance, while collaborating across PHY, Package,

Qualifications

• Bachelor’s degree with 6+ years of system/package design/technology engineering or related work experience.
• Master’s degree with 5+ years of system/package design/technology engineering or related work experience.
• PhD with 4+ years of system/package design/technology engineering or related work experience.

Responsibilities

• Perform package extraction for the time domain and frequency domain analysis.
• Perform system-level analysis for DDR, SerDes & mixed signal interfaces.
• Provide design guidelines for package design.
• Perform system simulation and provide feedback for design optimization.
• Develop design & analysis flow and automate the process.
• Create technical documentation and presentations.

Skills

Signal integrity

Power integrity

System simulation

Leadership

Communication with PHY and PCB teams

Education

Bachelor’s degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field

Master’s degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field

PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field

Tools

MATLAB

HFSS

Q3D

Sentinel-PSI

Clarity

ADS

HSPICE

Cadence Allegro

Mentor Xpedition

Job description

The Qualcomm Package Electrical Team has an opening in signal integrity and power integrity. The candidate will work with package and IC designers to optimize the overall package design and perform system simulation to ensure all system level constraints are met prior to the package Tape-out.

The candidate is expected to communicate with PHY owners to understand IP specs and with PCB designers to assess the impact of ball assignment on system performance, while collaborating across PHY, Package,