Senior Principal SIPI Architect: High-Speed Packaging

Asteralabs; San Jose (CA); On-site; USD 203,000 - 230,000; Full time

Job summary

Asteralabs is seeking a Principal Package Signal & Power Integrity Engineer to oversee the architecture of next-generation connectivity products. You will be pivotal in leading simulation strategies and ensuring robust signal and power integrity across systems.

The ideal candidate should have over 10 years of relevant experience in signal and power integrity with strong backgrounds in high-speed interfaces. The role emphasizes collaboration within cross-functional teams to deliver high-performance semiconductor solutions.

Qualifications

• 10+ years of experience in signal integrity, power integrity, package electrical design.
• Expertise in high-speed SerDes, PCIe, CXL, Ethernet.
• Hands-on expertise with EM extraction tools.

Responsibilities

• Define package SIPI architecture for next-gen connectivity products.
• Perform SI and PI simulations using standard software.
• Lead cross-functional execution across technical teams.
• Drive simulation-to-measurement correlation strategy.

Skills

Signal integrity

Power integrity

High-performance semiconductor design

EM extraction

SIPI modeling

Education

10+ years in relevant field

Tools

ANSYS HFSS

Keysight ADS

Cadence Sigrity

3D Layout

Job description

Asteralabs is seeking a Principal Package Signal & Power Integrity Engineer to oversee the architecture of next-generation connectivity products. You will be pivotal in leading simulation strategies and ensuring robust signal and power integrity across systems.

The ideal candidate should have over 10 years of relevant experience in signal and power integrity with strong backgrounds in high-speed interfaces. The role emphasizes collaboration within cross-functional teams to deliver high-performance semiconductor solutions.