Senior Signal & Power Integrity Engineer

Qualcomm; San Diego (CA); On-site; USD 127,000 - 191,000; Full time

Job summary

Qualcomm Technologies, Inc. in California seeks an experienced Signal Integrity/Power Integrity engineer to own end-to-end SI/PI closure across programs from pre-silicon to production. You will define targets for high-speed interfaces and guide layout guidelines while aligning with product KPIs.

The role requires hands-on expertise with HFSS, Sigrity, HSPICE and related tools, and close collaboration with SoC, package, board, and OEM teams to drive design convergence and signoff decisions.

Qualifications

• Bachelor's degree in Electrical Engineering or related field and 2+ years of System/Package Design/Technology Engineering or related work experience.
• Master's degree in Electrical Engineering or related field and 1+ year of System/Package Design/Technology Engineering or related work experience.
• PhD in Electrical Engineering or related field.

Responsibilities

• Own end-to-end SI/PI closure for programs (pre-silicon → post-silicon → production).
• Define design targets and layout design guidelines for all high-speed interfaces.
• Influence architecture decisions early in product lifecycle.
• Ensure SI/PI alignment with product KPIs (performance, yield, power, cost).
• Ensure compliance to standards (JEDEC, PCI-SIG, MIPI, IEEE).
• Lead design reviews and signoff decisions.
• Drive correlation between pre-silicon models and silicon/lab data.
• Lead debug of eye collapse / jitter margin issues, crosstalk and power noise and silicon-package-board interactions.

Skills

SI/PI expertise

Jitter/noise analysis

Cross-functional collaboration

Education

B.S. in Electrical/related

M.S. in Electrical/related

PhD in Electrical/related

Tools

HFSS

ADS

Sigrity

CST

SIwave

HSPICE

Job description

Qualcomm Technologies, Inc. in California seeks an experienced Signal Integrity/Power Integrity engineer to own end-to-end SI/PI closure across programs from pre-silicon to production. You will define targets for high-speed interfaces and guide layout guidelines while aligning with product KPIs.

The role requires hands-on expertise with HFSS, Sigrity, HSPICE and related tools, and close collaboration with SoC, package, board, and OEM teams to drive design convergence and signoff decisions.