Senior Packaging Engineer – Next-Gen SoCs (Equity)

Velaura; Austin (TX); On-site; USD 200,000 - 500,000; Full time

Benefits offered by this job

Equity participation

Performance-based incentives

Comprehensive benefits

Job summary

Velaura is building next-generation compute technology for cloud, edge, and PhysicalAI. Our packaging role leads architecture and development from concept through production, collaborating with silicon, board, thermal, and manufacturing teams to deliver high-performance, manufacturable products.

The ideal candidate has deep experience in advanced semiconductor packaging, package-level SI/PI, and cross-functional optimization to balance performance, cost, and yield.

Qualifications

• Extensive experience in advanced semiconductor packaging for high-performance SoCs.
• Ability to balance performance, cost, and manufacturability across teams.
• Experience with signal integrity, power integrity, thermal, and reliability.

Responsibilities

• Own package architecture from concept through production for Velaura SoCs.
• Partner with architecture and silicon teams to co-optimize package, die, board, and system design for performance, power, cost, and manufacturability.
• Drive package technology selection, including flip-chip, advanced substrates, fan-out, and future multi-die integration approaches.
• Lead package design, bump planning, substrate definition, escape routing, and assembly interactions with OSAT and substrate vendors.
• Own package-level signal integrity and power integrity planning for high-speed interfaces including LPDDR, PCIe, Ethernet, and other high-speed I/O.
• Collaborate on thermal architecture, mechanical integration, reliability, DFM, and qualification.
• Work with foundry, assembly, substrate, and test partners to successfully deliver products to production.
• Help define Velaura's long-term packaging roadmap as future products evolve.

Skills

Package design

SI/PI

Multi-die integration

Foundry collaboration

Tools

OSAT coordination

Job description

Velaura is building next-generation compute technology for cloud, edge, and PhysicalAI. Our packaging role leads architecture and development from concept through production, collaborating with silicon, board, thermal, and manufacturing teams to deliver high-performance, manufacturable products.

The ideal candidate has deep experience in advanced semiconductor packaging, package-level SI/PI, and cross-functional optimization to balance performance, cost, and yield.