Silicon Packaging Technology Engineer

Meta; Sunnyvale (CA); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Reality Labs is seeking a Silicon Packaging Technology Engineer to drive advanced packaging technology from concept through productization for next-generation consumer hardware. The role requires deep expertise in packaging technologies, cross-functional collaboration with OSATs and vendors, and the ability to optimize designs under thermal and mechanical constraints.

The ideal candidate will have 12+ years in packaging development, strong DOE and data analysis skills, and a track record of

Qualifications

• Bachelor's degree in Computer Science, Electrical/Mechanical/Materials Engineering, or equivalent.
• 12+ years in advanced silicon packaging development, process integration, and manufacturing.
• Experience co-optimizing package architecture with mechanical and thermal constraints.
• Cross-functional collaboration with foundries, OSATs, substrate vendors, and ODMs.
• Experience taking products from concept to prototyping and production with specs, qualifications, and yield/cost optimization.
• Master's or PhD in a relevant engineering discipline.
• Experience with reliability testing and qualification (JEDEC standards).
• Strong DOE methodology and statistical data analysis skills.
• Experience performing failure analysis and root cause determination.

Skills

Cross-functional collaboration

Problem solving

Communication skills

Root cause determination

DOE methodology

Statistical data analysis

Package qualification with OSATs

Travel internationally

Packaging technology knowledge

Education

Bachelor's degree in Computer Science

Bachelor's degree in Electrical/Mechanical/Materials Engineering

Master's or PhD in a relevant engineering discipline

Tools

WLCSP

Fan-out RDL

WoW

CoW

PoP

SiP

Flip chip

3D stacking

Chip-package interaction (CPI)

Job description

Reality Labs is delivering Meta's vision through AI-powered wearable products. The compute performance, power efficiency, and form factor requirements demand custom silicon with cutting-edge packaging solutions. We are seeking a Silicon Packaging Technology Engineer to join our team and drive advanced packaging technology from concept through productization for next-generation consumer hardware.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 12+ years of experience in advanced silicon packaging development, process integration, and manufacturing
• Ability to work with mechanical and thermal constraints to co-optimize package architecture for demanding form factors
• Demonstrated cross-functional collaboration with internal teams and external partners (foundry, OSAT, substrate vendors, ODMs)
• Experience taking products from concept to prototyping and production, including manufacturing specifications, vendor qualifications, and yield/cost optimization
• Bachelor's degree in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, or a relevant technical field
• Master's or PhD degree in a relevant engineering discipline
• Experience with board-level and component-level reliability testing and qualification (JEDEC standards)
• Strong DOE methodology, statistical data analysis, and process characterization skills
• Experience driving failure analysis (FA) — including physical FA techniques, fault isolation, and root cause determination
• Excellent problem-solving and communication skills; the ability to influence cross-functional stakeholders
• Track record of successful complex package product qualification with OSATs
• Experience with a broad range of packaging technologies: WLCSP, fan-out RDL, WoW, CoW, PoP, SiP, flip chip, and 3D stacking
• Strong understanding of chip-package interaction (CPI), thermo-mechanical stress, and warpage management
• Ability to work independently, manage multiple programs, and travel internationally (typically once per quarter)