Senior Packaging Engineer – Chip Package Design & Equity

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 322,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA in Santa Clara, CA, invites highly experienced hardware engineers to join our silicon packaging team. You will define and implement the chip pad ring and substrate interconnect schemes, leading the package layout design with a world-class electrical package mindset.

You will collaborate with Circuit, SI, RTL, Place and Route, substrate layout, and system design teams to deliver robust, high-performance packaging solutions.

Qualifications

• BSEE or equivalent experience.
• 8+ years in board/system design; package design experience a plus.
• Strong understanding of transmission line theory, power delivery and signal integrity.
• Scripting skills in Perl, Python, Tcl; Cadence and Excel knowledge beneficial.
• Hardworking and able to work with minimal supervision.
• Desire to solve complex technical problems.

Responsibilities

• Define and implement the chip pad ring and lead the package layout design process.
• Collaborate with teams across Circuit, SI, RTL, Place & Route, substrate layout and system design.
• Define a chip floor plan, pad ring, substrate, and ball-out implementing a robust world-class electrical package.
• Communicate effectively with various teams throughout the company.

Skills

Signal integrity

Independent work

Problem solving

Team collaboration

Education

BSEE or equivalent

Tools

Perl

Python

Tcl

Cadence

EXCEL

Job description

NVIDIA in Santa Clara, CA, invites highly experienced hardware engineers to join our silicon packaging team. You will define and implement the chip pad ring and substrate interconnect schemes, leading the package layout design with a world-class electrical package mindset.

You will collaborate with Circuit, SI, RTL, Place and Route, substrate layout, and system design teams to deliver robust, high-performance packaging solutions.