Senior Packaging Engineer for AI Accelerators (Multi‑Die)

Entrada Ventures; Palo Alto (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Equity

Benefits

401k

Job summary

Entrada Ventures seeks a Senior Packaging Engineer in the Silicon Valley area to architect and deliver advanced multi‑die IC packages for high‑performance AI accelerators. This role focuses on package architecture, substrate design, manufacturability, and vendor engagement.

The candidate will define stack‑ups, engage with fabrication partners, and collaborate with IC design teams to ensure system‑level alignment and reliability across next‑generation products.

Qualifications

• B.S./M.S. in Electrical Engineering or related field.

Responsibilities

• Select and design optimal multi‑die package types (MCM, 2.5D, 3D, fan‑out, CoWoS, InFO, CPC, CPO).
• Define package specifications, bump map and ball map, interposer requirements, and mechanical constraints.
• Define substrate stack‑ups, bump pitch, ball pitch, routing, via structures, and material choices.
• Perform high‑speed signal escaping, routing and power distribution network design.
• Manage subcontractors and work directly with TSMC and/or OSAT on bumping, substrate options, and advanced packaging flows.
• Partner with IC design, physical design, SI/PI, and board teams to ensure package requirements meet system‑level needs.
• Evaluate emerging packaging technologies and drive adoption for next‑generation products.
• Support package‑level bring‑up, failure analysis, debug and qualification.

Skills

Multi‑die package design

UCIe integration

Substrate materials understanding

SI/PI concepts

Packaging subcontractors management

Interface with TSMC/OSAT

Package modeling tools

Education

B.S./M.S. in Electrical Engineering

Tools

HFSS

Sigrity

Job description

Entrada Ventures seeks a Senior Packaging Engineer in the Silicon Valley area to architect and deliver advanced multi‑die IC packages for high‑performance AI accelerators. This role focuses on package architecture, substrate design, manufacturability, and vendor engagement.

The candidate will define stack‑ups, engage with fabrication partners, and collaborate with IC design teams to ensure system‑level alignment and reliability across next‑generation products.