Staff Memory Verification Engineer - SystemVerilog/UVM

SmartRecruiters, Inc.; Duluth (GA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical benefits

Dental & vision

Paid time off

Life insurance

Job summary

Renesas is seeking an experienced Staff Design Verification Engineer to join our team focused on memory interface products for data center, AI, and cloud computing applications. You will verify advanced memory data buffer products, including DDR6 and future generations, using SystemVerilog/UVM environments and testbenches.

Ideal candidates bring 8+ years in semiconductor design verification, strong SystemVerilog/UVM expertise, and a track record of owning complex verification assignments from

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 8+ years of related experience in semiconductor design verification.
• Strong proficiency with SystemVerilog and hands-on experience using UVM (Universal Verification Methodology).
• Experience developing and debugging UVM-based verification environments and testbenches.

Responsibilities

• Drive verification activities for complex digital designs at the block and system level.
• Develop and execute verification plans based on functional and performance specifications.
• Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches.
• Develop verification tests, functional coverage, checkers, and other verification components.
• Take ownership of verification environments and verification execution for assigned blocks and features.

Skills

SystemVerilog

UVM

DDR memory experience

Analytical thinking

Education

Bachelor's or Master's in Electrical Engineering/Computer Engineering/Computer Science

Tools

Testbenches

Verification environments

Job description

Renesas is seeking an experienced Staff Design Verification Engineer to join our team focused on memory interface products for data center, AI, and cloud computing applications. You will verify advanced memory data buffer products, including DDR6 and future generations, using SystemVerilog/UVM environments and testbenches.

Ideal candidates bring 8+ years in semiconductor design verification, strong SystemVerilog/UVM expertise, and a track record of owning complex verification assignments from