Senior Digital Verification Engineer - Data Buffer DDR6

Renesas; Duluth (GA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical insurance

Health savings account

Dental

Vision

Flexible spending accounts

Life insurance

AD&D

Pet insurance

Company-paid life insurance and AD&D

LTD

Short term medical benefits

Paid sick time

Paid holidays

Accrued paid vacation

Job summary

Renesas is seeking a seasoned verification engineer to lead the DDR6 data buffer memory interface verification for data centers and AI/cloud workloads. You will own the verification environments, write test plans, and collaborate with design teams to ensure correctness and performance across DDR5/DDR6 generations.

The role emphasizes reusable UVM-based testbench development, thoughtful verification strategy, and ongoing process improvements to maximize efficiency and quality in a fast-paced,

Qualifications

• Masters in Electrical Engineering or Computer Engineering with 7+ years of experience.
• Bachelor's Degree in Electrical Engineering or Computer Engineering with 9+ years of experience.

Responsibilities

• Drive the Memory interface products verification effort, including defining the verification strategy, developing test plans, coverage, and executing tests.
• Drive and quality control the creation of a verification test plan.
• Work closely with the design team to ensure that the design meets the requirements and is testable.
• Identify and drive improvements to the verification process to ensure the highest levels of quality and efficiency.
• Drive and monitor coverage of design verification.
• Provide regular updates to management on the status of the verification effort.

Education

Masters in Electrical Engineering or Computer Engineering

Bachelor's Degree in Electrical Engineering or Computer Engineering

Tools

UVM

Job description

Renesas is seeking a seasoned verification engineer to lead the DDR6 data buffer memory interface verification for data centers and AI/cloud workloads. You will own the verification environments, write test plans, and collaborate with design teams to ensure correctness and performance across DDR5/DDR6 generations.

The role emphasizes reusable UVM-based testbench development, thoughtful verification strategy, and ongoing process improvements to maximize efficiency and quality in a fast-paced,