Senior Mask Layout Engineer: Mixed-Signal & FinFET Focus

NVIDIA Corporation; Santa Clara (CA); On-site; USD 132,000 - 236,000; Full time

Job summary

NVIDIA in Santa Clara, CA, is seeking a Senior Mask Layout Design Engineer to join our Dynamic team responsible for high-speed mixed-signal circuit layouts. You will perform physical layout for PLLs, high-speed I/O, and general analog layouts in sub-micron CMOS, collaborate with ASIC and mixed-signal engineers, and verify against design rules and schematics.

Requirements include a BSEE (MSEE a plus), 8+ years of mask design experience, FinFET tape-out, familiarity with TSMC N5/N4/N3, Cadence

Qualifications

• 8+ years of mask design and layout experience in sub-micron CMOS.
• BSEE required; MSEE is a plus.
• Tape-out experience with FinFET technology; knowledge of TSMC N5/N4/N3 preferred.
• Proficiency with Cadence tools, especially Virtuoso; DRC/LVS with Calibre.

Responsibilities

• Perform physical layout for mixed-signal functions (PLLs, high-speed I/O, analog blocks).
• Collaborate with ASIC and mixed-signal engineers to tailor designs for integration in VLSI products.
• Floor planning, custom layout, and verification against design rules and schematics.

Skills

Analog/mixed-signal layout

Team collaboration

Scripting (Perl, Python)

Problem solving

Education

BSEE or equivalent

MSEE (a plus)

Tools

Cadence Virtuoso

ICV/Calibre

Submicron CMOS processes

Job description

NVIDIA in Santa Clara, CA, is seeking a Senior Mask Layout Design Engineer to join our Dynamic team responsible for high-speed mixed-signal circuit layouts. You will perform physical layout for PLLs, high-speed I/O, and general analog layouts in sub-micron CMOS, collaborate with ASIC and mixed-signal engineers, and verify against design rules and schematics.

Requirements include a BSEE (MSEE a plus), 8+ years of mask design experience, FinFET tape-out, familiarity with TSMC N5/N4/N3, Cadence