Senior Mask Layout Engineer - Analog/High-Speed, Equity

NVIDIA Corporation; Santa Clara (CA); Sur place; USD 132 000 - 207 000; Plein temps

Résumé du poste

NVIDIA Corporation in Santa Clara, CA is seeking a Senior Mask Layout Design Engineer to join a high-speed mixed-signal team. You will perform physical layout for analog/digital blocks and work with ASIC/mixed-signal engineers to enable sub-micron CMOS designs.

Responsibilities include floor planning, custom layout, and verification against design rules and schematics using Cadence tools; you will contribute to VLSI integration and process technology efforts.

Qualifications

• BSEE or equivalent experience and 8+ years in the industry.
• Deep understanding of analog layout concepts in submicron CMOS.
• Proficiency with Cadence custom tools and knowledge of DRC/LVS flows.
• Experience with verification tools such as Dracula, Hercules, Calibre, and PrimeYield.
• Proficient in scripting languages like Perl and Python.

Responsabilités

• Perform physical layout for mixed-signal functions like PLLs, high-speed SerDes, and ADCs using Cadence tools.
• Collaborate with ASIC and mixed-signal engineers to customize designs for VLSI product integration.
• Participate in floor planning, custom layout, and verification against design rules and schematics.

Connaissances

Analog layout concepts

Cadence tools

Scripting: Perl/Python

DRC/LVS flows

Team collaboration

Formation

BSEE or equivalent

Outils

Cadence

Dracula

Hercules

Calibre

PrimeYield

Description du poste

NVIDIA Corporation in Santa Clara, CA is seeking a Senior Mask Layout Design Engineer to join a high-speed mixed-signal team. You will perform physical layout for analog/digital blocks and work with ASIC/mixed-signal engineers to enable sub-micron CMOS designs.

Responsibilities include floor planning, custom layout, and verification against design rules and schematics using Cadence tools; you will contribute to VLSI integration and process technology efforts.