Senior Mask & Layout Design Engineer — Submicron CMOS

NVIDIA; Oregon; On-site; USD 108,000 - 184,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA seeks a Senior Mask Design Engineer in Oregon to join a dynamic team focused on advanced packaging solutions. You will collaborate with PTL and I/O engineers, performing physical layout for silicon interposers using Cadence tools to meet tight schedules.

The role requires a BS in Electrical Engineering and 3+ years of mask and layout design experience, with expertise in Cadence Virtuoso and LVS/DRC workflows.

Qualifications

• B.S. in Electrical Engineering or equivalent.
• 3+ years of mask and layout design experience.
• Deep understanding of submicron CMOS layout concepts.
• Proficiency with Cadence tools, especially Virtuoso.
• Experience with DRC/LVS and custom deck customization.

Responsibilities

• Collaborate with PTL and I/O signal integrity and tech engineers to deliver package solutions on tight schedules.
• Perform physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies for package size, cost, and system performance.
• Study layout floorplans and perform custom layout verification against rules and netlists.
• Propose layout trade-offs to PTL for resolution and implementation.

Skills

Mask design

Layout design

Cadence Virtuoso

Perl/Python scripting

DRC/LVS workflows

APD packaging tools

Education

B.S. Electrical Engineering

Tools

Cadence tools

Virtuoso

Calibre

ICV/Thunder

Job description

NVIDIA seeks a Senior Mask Design Engineer in Oregon to join a dynamic team focused on advanced packaging solutions. You will collaborate with PTL and I/O engineers, performing physical layout for silicon interposers using Cadence tools to meet tight schedules.

The role requires a BS in Electrical Engineering and 3+ years of mask and layout design experience, with expertise in Cadence Virtuoso and LVS/DRC workflows.