Senior Mask Layout Engineer – Mixed-Signal & High-Speed

NVIDIA; Austin (TX); On-site; USD 132,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA seeks a Senior Mask Layout Design Engineer to join our Dynamic team in Austin. You will perform physical layout for mixed-signal functions, collaborating with ASIC and mixed-signal engineers to tailor designs for VLSI integration.

The role requires 8+ years of mask design experience, FinFET/tape-out experience with TSMC nodes, Cadence Virtuoso proficiency, and strong analog layout fundamentals. NVIDIA offers equity, comprehensive benefits, and a commitment to diversity.

Qualifications

• Hold a BSEE or equivalent experience. MSEE is a plus.
• 8+ years of relevant mask design / layout experience.
• Tape-out experience with FinFET technology is required. Experience with TSMC N5/N4/N3 is preferred.
• Experience with high-speed SerDes/RF layout design is helpful and Experience with top level integration would be excellent to have.
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies
• Validated experience with Cadence custom circuit design tools - particularly virtuoso
• Experience running and debugging DRC and LVS with verification tools such as ICV/Calibre
• Ability to work optimally in a team, good interpersonal skills and positive energy.
• Proficiency in scripting languages like perl, python, skill etc. is a plus
• Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks

Responsibilities

• Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools
• You’ll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products and Job duties will include floor planning, custom layout and verifying against design rules and schematics.

Skills

Analog/mixed-signal layout

SerDes/RF layout

Floor planning

Scripting (Perl, Python)

Team collaboration

DRC/LVS debugging

Knowledge of DRC/LVS flows

Education

BSEE or equivalent

MSEE

Tools

Cadence Virtuoso

Calibre

Job description

NVIDIA seeks a Senior Mask Layout Design Engineer to join our Dynamic team in Austin. You will perform physical layout for mixed-signal functions, collaborating with ASIC and mixed-signal engineers to tailor designs for VLSI integration.

The role requires 8+ years of mask design experience, FinFET/tape-out experience with TSMC nodes, Cadence Virtuoso proficiency, and strong analog layout fundamentals. NVIDIA offers equity, comprehensive benefits, and a commitment to diversity.