Senior Logic Design Engineer: Cache Coherent Interconnects

Nvidia Corporation; Santa Clara (CA); On-site; USD 136,000 - 218,500; Full time

Benefits offered by this job

Equity options

Comprehensive benefits package

Job summary

A leading technology company in Santa Clara is seeking a Senior Logic Design Engineer to design CPU on-chip and off-chip interconnect networks. The role involves owning and delivering a chip unit, writing performant RTL, and collaborating closely with verification teams. Candidates should have a Master's degree and 5+ years of relevant experience, particularly in processor designs and ASIC flow. The competitive salary ranges from $136,000 to $218,500 for Level 3, and $168,000 to $264,500 for Level 4, along with equity and benefits.

Qualifications

• 5+ years of experience in processor or related high-performance semiconductor designs.
• Deep understanding of RTL design, verification, logic synthesis, prototyping, DFT, timing analysis.
• Background in computer architecture, cache coherency or high-speed interconnects is helpful.

Responsibilities

• Own and deliver a specific unit on the chip.
• Write high-performance, low-power RTL, synthesis and timing closure.
• Collaborate with the verification team to ensure correctness.

Skills

Verilog expertise

Strong communication skills

Mentoring junior engineers

Education

Master's Degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

ASIC design flow

Job description

A leading technology company in Santa Clara is seeking a Senior Logic Design Engineer to design CPU on-chip and off-chip interconnect networks. The role involves owning and delivering a chip unit, writing performant RTL, and collaborating closely with verification teams. Candidates should have a Master's degree and 5+ years of relevant experience, particularly in processor designs and ASIC flow. The competitive salary ranges from $136,000 to $218,500 for Level 3, and $168,000 to $264,500 for Level 4, along with equity and benefits.