ASIC Logic Design Engineer – RTL, Timing, Interconnect

NVIDIA; Santa Clara (CA); On-site; USD 100,000 - 189,750; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Santa Clara is seeking a Logic Design Engineer to join the CPU Logic Design Team. You will define micro-architectural aspects of on‑chip interconnect, coherency and last‑level caches, and contribute to RTL coding, synthesis and timing closure.

You will deliver a focused unit, write high‑quality RTL, collaborate with verification and implementation teams to meet timing, area and power goals, and support lab debug and bring‑up.

Qualifications

• BS or MS in Electrical/Computer Engineering or Computer Science.
• Experience in processor or high-performance semiconductor designs.
• Verilog expertise and understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up and lab debug.
• Effective communication and interpersonal skills, with a track record of mentoring junior engineers and interns.
• Strong background in computer architecture, cache coherency or high-speed interconnects.

Responsibilities

• Own and be responsible for crafting and timely delivery of a specific unit on the chip.
• Write readable, high‑performance and low‑power RTL, perform synthesis and timing closure, and produce design documentation.
• Collaborate with the verification team to validate the correctness of your unit.
• Work with implementation to achieve timing, area, performance and power goals.
• Assist with timing closure of super units.

Skills

Verilog

RTL design

timing analysis

DFT

lab debug

mentoring

Education

BS or MS in Electrical/Computer Engineering or Computer Science

Job description

NVIDIA in Santa Clara is seeking a Logic Design Engineer to join the CPU Logic Design Team. You will define micro-architectural aspects of on‑chip interconnect, coherency and last‑level caches, and contribute to RTL coding, synthesis and timing closure.

You will deliver a focused unit, write high‑quality RTL, collaborate with verification and implementation teams to meet timing, area and power goals, and support lab debug and bring‑up.