Senior CPU Cache & RTL Engineer—Microarchitecture

Apple Inc.; Santa Clara (CA); On-site; USD 181,100 - 318,400; Full time

Benefits offered by this job

Comprehensive medical and dental coverage

Retirement benefits

Discounted products and services

Educational expense reimbursement

Discretionary bonuses or commission payments

Job summary

A leading tech company in Santa Clara seeks an experienced engineer to drive CPU cache subsystem architecture and RTL development. The ideal candidate should have a Bachelor's degree and over 10 years of experience in microprocessor architecture, with skills in Verilog or VHDL, and strong logic design principles. Benefits include competitive salary between $181,100 and $318,400, stock options, comprehensive medical coverage, and educational reimbursement.

Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Experience with microprocessor architecture.
• Experience with logic design principles with timing and power implications.
• Understanding of low power microarchitecture techniques.

Responsibilities

• Drive CPU multi-level cache subsystem architecture.
• Develop RTL design to target power, performance, area, and timing goals.
• Support the verification team in functional verification.
• Implement and verify physical design aspects including timing and reliability.

Skills

Microprocessor architecture

Logic design principles

Verilog or VHDL

Simulation and debugging

C or C++ programming

Python or Perl

Education

Bachelor's degree in relevant field

Job description

A leading tech company in Santa Clara seeks an experienced engineer to drive CPU cache subsystem architecture and RTL development. The ideal candidate should have a Bachelor's degree and over 10 years of experience in microprocessor architecture, with skills in Verilog or VHDL, and strong logic design principles. Benefits include competitive salary between $181,100 and $318,400, stock options, comprehensive medical coverage, and educational reimbursement.