Senior ASIC PD Engineer — Cache Coherent Interconnects

NVIDIA AI; Eugene (OR); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking engineers for the CPU Cache Coherent Interconnects Design Team to drive physical design of the on-chip interconnect network and last-level caches, with responsibilities across synthesis, timing closure, and collaboration with logic teams on micro-architecture feasibility.

The role requires a Master’s degree and 5+ years in high-performance semiconductor design, with strong Verilog expertise and experience in RTL, DFT, and ECO.

Qualifications

• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 5+ years of experience in processor or other related high-performance semiconductor designs.
• Physical design expertise in high-frequency design, including hands-on synthesis experience, timing analysis, floor-planning and in-depth knowledge of industry standard physical design tools is required.
• Experience in interconnect/cache/core design is desirable.
• Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

Responsibilities

• As a member of our CPU team, you'll be responsible for synthesis and achieving timing, area, performance and power goals of the on-chip interconnect network and last-level caches.
• Help evaluate the physical design for next-generation Nvidia coherent interconnects and system-level caches.

Skills

Verilog

Strong communication

Education

Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science

Tools

Physical design tools

Job description

NVIDIA is seeking engineers for the CPU Cache Coherent Interconnects Design Team to drive physical design of the on-chip interconnect network and last-level caches, with responsibilities across synthesis, timing closure, and collaboration with logic teams on micro-architecture feasibility.

The role requires a Master’s degree and 5+ years in high-performance semiconductor design, with strong Verilog expertise and experience in RTL, DFT, and ECO.