Lead Cache Coherency Architect: NoC & IP Co-design (Equity)

NVIDIA Corporation; Santa Clara (CA); On-site; USD 152,000 - 287,500; Full time

Job summary

A leading semiconductor company is looking for a Senior Cache Coherency Architect in Santa Clara, CA. This role involves defining interconnect architecture and cache-coherency protocols and collaborating with architects to meet project requirements. Candidates should have a Master's degree, 5+ years of experience in processor design, and strong understanding of cache coherency protocols. The position offers a competitive base salary range between 152,000 USD - 287,500 USD, eligible for equity, and applications accepted until April 24, 2026.

Qualifications

• 5+ years of experience in processor design or high-performance semiconductor designs.
• Hands-on experience in industry-standard protocols (e.g., AXI, ACE, CHI).
• Experience authoring specifications and designing cache-coherent interconnects.

Responsibilities

• Define interconnect architecture and cache-coherency protocols.
• Contribute to interconnect IP block specifications and integration.
• Collaborate with architects to meet project power, performance, and area requirements.

Skills

Cache coherency

Processor design

C/C++ programming

Python

Verilog

Education

Master's degree in electrical engineering, Computer Engineering, or Computer Science

Job description

A leading semiconductor company is looking for a Senior Cache Coherency Architect in Santa Clara, CA. This role involves defining interconnect architecture and cache-coherency protocols and collaborating with architects to meet project requirements. Candidates should have a Master's degree, 5+ years of experience in processor design, and strong understanding of cache coherency protocols. The position offers a competitive base salary range between 152,000 USD - 287,500 USD, eligible for equity, and applications accepted until April 24, 2026.