Interconnect Design Engineer: TileLink & Coherence Expert

SiFive, Inc.; Santa Clara (CA); On-site; USD 158,760 - 194,040; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Job summary

SiFive, Inc. is looking for a staff level hardware engineer to design industry-leading CPU and interconnect IP. You will work in a dynamic environment, building multiple CPU lines and TileLink interconnects.

This role requires strong expertise in cache architectures and hardware design, with additional skills in software engineering. The position offers a competitive base pay ranging from $158,760 to $194,040, along with a comprehensive benefits package.

Qualifications

• Strong knowledge of cache architectures and NoC.
• Proficient in bus protocols and hardware design.
• Experience with software engineering principles.

Responsibilities

• Architect and implement TileLink interconnects and controllers.
• Enhance designs for efficiency and performance.
• Work collaboratively and document knowledge.

Skills

Cache and cache coherency architectures

NoC or other interconnect fabrics

Industry-standard bus protocols (AXI, AHB, APB, CHI)

Object-oriented programming

Functional programming

Verilog/System-Verilog/VHDL design

Attention to detail

Teamwork

Education

BS/MS in EE, CE, CS or related discipline

Tools

Git/GitHub

Jira

Confluence

Job description

SiFive, Inc. is looking for a staff level hardware engineer to design industry-leading CPU and interconnect IP. You will work in a dynamic environment, building multiple CPU lines and TileLink interconnects.

This role requires strong expertise in cache architectures and hardware design, with additional skills in software engineering. The position offers a competitive base pay ranging from $158,760 to $194,040, along with a comprehensive benefits package.